1. Field of the Invention
The present invention relates to a high density integrated circuit packages and the method for forming the same, and more particularly to a high density integrated circuit flip chip packages and the method for forming the same.
2. Description of the Related Art
Integrated circuit package technologies are continually developed toward demands of micro-size and high integration in the integrated circuit industrial sector. The improvements focus on the integration of millions of transistors, devices and circuits on a silicon substrate.
Through a serious of precise and fine-tune processes such as etching, implantation, deposition and dicing in various processing equipments, integrated circuits are formed on wafers. Each processed wafer includes a plurality of chips and each chip can be packaged by a surrounding molding compound and connect to outside via pins. Package examples include a M dual-in-line package (M-dip) having two rows of pins connecting the chip and a printed circuit board (PCB) through the bottom of the package structure. Other package examples for high density PCB include a single-in-line package (SIP) and a small outline J-leaded package (SOJ).
Integrated circuit package can be sorted by chip number in a package assembly. A single chip package (SCP) and a multichip package (MCP) are two major sorts and the MCP includes a multichip module (MCM). Integrated circuit package can also be sorted by mounting types which comprise a pin-through-hole (PTH) type and a surface mount technology (SMT). The pins of the PTH type could be thin pins or thin metal plates. The thin pins or the thin metal plates are inserted and joint mounting into vias of a PCB when the chip is mounted. Chips with SMT packages are adhered on a PCB and then are soldered during mounting. In order to reduce the volume of an integrated circuit package and increase the integration of the chip, a more advanced direct chip attach (DCA) package is applied. The DCA package technology mounts an integrated circuit chip on a substrate directly and then completes the electrical connection.
Wire-bonding packages are most commonly used at present time. Firstly, a chip is mounted on a lead frame. Then bonding wires are utilized to connect the chip and the lead frame, and a molding compound is applied to cover the chip and portions of the lead frame to complete the package. The lead frame with the chip is attached and mounted on a substrate such as a printed circuit board (PCB) to connect circuits of the chip and the PCB. However, since the wire-bonding package technologies are limited to the package size, flip chip package technologies are developed to meet the requirements of size shrinking. First of all, the flip chip package technologies mount chips having solder bumps thereon on a substrate. Then an underfill material is filled into the space between the chips and the substrate to protect the joint connections and the chips. The size of the flip chip packages can be further minimized without using any lead frame. Nevertheless, since the flip chip package technologies use solder masks to protect circuit traces on a package substrate from short circuit stemming from the contact between solder bumps and the circuit traces, several drawbacks such as misalignment resulting from the solder masks during the bonding of chips and the substrate via solder bumps are still to be overcame.
Conventional flip chip packages comprise solder mask defined (SMD) and non-solder mask defined (NSMD) flip chip packages. Referring to FIG. 1, a chip is mounted on a substrate by SMD and underfilling. The package structure in FIG. 1 includes a substrate 10 having circuit traces 25, bump pads 20 and a solder mask 30, and a chip 40. The chip 40 has solder bumps 15 thereon. The chip 40 is bonded to the substrate 10 via the bonding of the solder bumps 15 and the bump pads 20. The substrate 10 further comprises solder balls 17 or pins (not shown) used to electrically connect other devices. An underfill material 50 is formed between the chip 40 and the substrate 10 to protect the connection of the solder bumps 15 and the bump pads 20 from being contaminated and consolidate the connection.
The solder mask 30 covers the circuit traces 25 in order to avoid short circuit induced by overflow of the solder bumps 15. The solder mask 30 has a plurality of openings smaller than the bump pads 20 to expose the bump pads 20. However, since the bump pads 20 must have additional space in peripheral areas to tolerate the misalignment of the solder bumps 15, the margin space between adjacent bump pads 20 would be limited. Therefore, the number of circuit traces passing the margin space is also limited. Furthermore, for NSMD packages, the openings of solder mask are larger than bump pads and more margin space between adjacent bump pads would be needed to tolerate the misalignment of the solder bumps so that the number of circuit traces passing the margin space is also limited. Thus the conventional flip chip package structures set forth would not meet the requirement of size minimization due to the limited density of circuit layout.
Moreover, the processes for forming solder mask including photolithography and etching process increase complexity and production cost of package process. The misalignment of solder mask further degrades quality of integrated circuit package structures. The weak bonding between applied underfill material and the solder mask could result cracks and peeling off of the solder mask, and degrade the reliability of integrated circuit package structures.